The present invention relates in general to data communication systems, and more particularly, to a method and apparatus for optimizing analog bias current for minimizing power consumption in circuits used in data communication systems.
Most electronic devices like TV""s, stereos, and computers need integrated circuits work properly. Today""s wireless communications markets are being driven by a multitude of benefits derived from these circuits. These markets include products such as cellular phones, cordless phones, pagers, and the like have freed corporate and individual users from their desks and homes and are driving the demand for additional equipment and systems to increase their utility. Consequently, data transmission products will play an increasingly important role in the overall communications infrastructure in the next decade.
Mixed-signal integration and power management have taken on added importance now that analog and mixed analog-digital ICs have become the fastest-growing segment of the semiconductor industry. Integration strategies for multimedia consoles, cellular telephones and battery-powered portables are being developed, as well as applications for less integrated but highly specialized building blocks that serve multiple markets. These building blocks include drivers, data converters, filters, amplifiers and processors.
One aspect of data transmission devices in today""s telecommunication industry is designing integrated circuits with lower power consumption and exceptional performance characteristics. The soaring popularity of powerful cellular telephones and laptop computers drives manufacturers to develop smaller communication devices utilizing these circuits. A continuing goal of the ever-developing communication industry is to design smaller, faster, and lower power consuming devices. Nevertheless, some barriers must be overcome to achieve this goal.
One of the barriers is to minimize the amount of power consumption in analog circuits without degrading the performance of critical analog circuits. Typically, a large amount of power is consumed due to the required amount of bias current used in analog circuits. For example, the amount of bias current for analog circuits is generally set in such a way that the performance of the analog circuits would meet required performance specification in the worst silicon fabrication condition. Often time, it is not necessary to have such amount of bias current but the performance of the analog circuits would still meet required performance specification. Accordingly, this causes the power consumption of analog circuits to be more than what it could be for most silicon fabrication condition.
It is with respect to these or other considerations that the present invention has been made.
In accordance with the present invention, the above and other problems are solved by providing an analog bias current optimization circuitry. The analog bias current optimization circuitry in accordance with the principles of the present invention is capable of minimizing power consumption in analog circuits without degrading the performance of the circuits.
In one embodiment of the present invention, an analog bias current optimization circuitry includes a transmit digital signal processor (TX-DSP) to generate a signal pattern; a plurality of analog circuits to convert data between a digital format and an analog format, to transmit the analog data to a transmission line, and to receive the analog data from the transmission line, the signal pattern being sent to the analog circuits; a receive digital signal processor (RX-DSP) to receive an output signal from the analog circuits; and a controller, based on a captured signal from the RX-DSP, to evaluate signal quality degradation of the analog circuits and adjust a bias current of the analog circuits without causing signal quality degradation.
Further in one embodiment of the present invention, the evaluation of signal quality degradation and adjustment of the bias current of the analog circuits can be performed continuously by the controller.
Still in one embodiment of the present invention, the RX-DSP includes an echo canceller (EC). A residual echo or echo error of the EC is evaluated by the controller.
Additional in one embodiment of the present invention, the RX-DSP includes a decision feedback equalizer (DFE). A DFE error is evaluated by the controller.
Yet in one embodiment of the present invention, the analog bias current optimization circuitry includes a switch. The switch switches between a first position wherein the signal received by the RX-DSP is only from the analog circuits, and a second position wherein the signal received by the RX-DSP is hybrid, i.e. from both the analog circuits and the transmission line.
In one embodiment of the present invention, a method of optimizing analog bias current includes generating a signal pattern by a transmit digital signal processor (TX-DSP); sending the signal pattern to a plurality of analog circuits which convert data between a digital format and an analog format, transmit the analog data to a transmission line, and receive the analog data from the transmission line; receiving an output signal from the analog circuits by a receive digital signal processor (RX-DSP); and evaluating signal quality degradation of the analog circuits from a captured signal in the RX-DSP and adjusting a bias current of the analog circuits without causing signal quality degradation, by a controller, based on the captured signal from the RX-DSP.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.